1. Field of the Invention
This invention relates to a video signal processing device, and more particularly, to a video signal processing device using a random access memory (RAM).
2. Description of the Prior Art
Heretofore, in a circuit for providing a freezing function of a digital image signal and a so-called frame synchronizing function using a random access memory (RAM), the two functions have been provided in separate memory circuits, respectively, because address control, memory capacity and the like differ between a RAM for performing the freezing function and a RAM for performing the frame synchronizing function.
That is, in a circuit for providing the freezing function, there is provided a RAM having a memory capacity for the amount of at least one frame (field). In a case other than a frozen state, image data which have previously been digitized are sequentially written using one address at every one cycle time of the RAM. When image data are passed through the RAM, that is, when freezing is not performed, image data are similarly sequentially read while performing data writing. When freezing is performed, the writing of image data is stopped, and image data for the amount of one frame (which have been input immediately before the stoppage) are sequentially and repeatedly read.
In a circuit for providing the frame synchronizing function, there is provided a RAM having a memory capacity for the amount of at least one frame. In order to prevent the write and read timings of image data for the RAM from gradually deviating due to differences in the clock systems, and to prevent the write and read addresses overlapping each other, a method is adopted in which a deviation between the write and read timings is detected according to a difference between the write and read addresses. Then, the write or read address is skipped when the deviation becomes equal to or larger than a certain threshold value. From the viewpoint of the skipping of the address and the deviation of write and read timings, the RAM for providing the frame synchronizing function usually has a memory capacity of two frames.
As described above, the RAM for providing the freezing function has a memory capacity of at least one frame, the RAM for providing the frame synchronizing function has a memory capacity of two frames, and a dedicated memory control circuit is coupled to each RAM. Hence, the configuration of the control circuit is complicated. Furthermore, a memory capacity as large as three frames is required.